Release:

2019, Vol. 5. №1Title:

Implementation of discrete cosinus transformation in the input block of the memristor neural processor
Author:
Alexander D. Pisarev

For citation:
Pisarev A. D. 2019. “Implementation of discrete cosinus transformation in the input block of the memristor neural processor”. Tyumen State University Herald. Physical and Mathematical Modeling. Oil, Gas, Energy, vol. 5, no 1, pp. 147-161. DOI: 10.21684/2411-7978-2019-5-1-147-161

About the author:

Alexander D. Pisarev, Cand. Sci. (Tech.), Associate Professor, Department of Applied and Technical Physics, Head of Laboratory of Beam-Plasma Technologies, SEC “Nanotechnologies”, University of Tyumen; eLibrary AuthorID, ORCID, Scopus AuthorID, spcb.doc@gmail.comAbstract:

This article describes a study on the border of neural network information technologies and memristor nanoelectronics of processors. From the point of view of information technology, artificial and more complex biomorphic neural networks are learning architectures consisting of a large number of simple solvers. The distribution of a large number of simple calculations decreases the performance consumption of even the most powerful standard processor systems. Therefore, in the development of neural networks, the task of creating a neural processor has become particularly urgent.

Neuroprocessor is understood as hardware specifically designed to implement the neural network model in an efficient manner. Major electronics manufacturers (including IBM, Google, Intel, and Huawei) have already joined the neuroprocessor creation race. The tasks of this direction require not only the developed silicon technologies, but also the use of new elements of nanoelectronics, including memristors.

This paper describes the adaptation to hardware of one of the variants of fast discrete cosine transform algorithms, which is a type of Fourier method. The importance of this study lies in the need to solve the problem of entering standard information into the neural processor.

As a hardware, a 3D logical matrix is used, implemented on nano-technological elements of the combined memristor-diode crossbar electronics. This paper presents a method for increasing the filtering rate by applying simple operations that are performed in parallel in logical connected blocks of super-large 3D logic matrix. The speed of such a system can be extremely high and is determined by the time of one clock pulse, limited only by the speed of operation of the inverter elements and the propagation of signals on the tires of the combined memristor-diode crossbar.

Keywords:

References:

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