Release:2018, Vol. 4. №3
About the author:Alexander D. Pisarev, Cand. Sci. (Tech.), Associate Professor, Department of Applied and Technical Physics, Head of Laboratory of Beam-Plasma Technologies, SEC “Nanotechnologies”, University of Tyumen; eLibrary AuthorID, ORCID, Scopus AuthorID, email@example.com
This research relates to the industry of creating nanoelectronic blocks intended for the implementation of a neuroprocessor, which is a hardware platform of neural networks and complex biomorphic architectures, which may, for example, simulate the work of the cortical column of the brain. This article describes the scheme of the electronic logic block, which is the key node of the neuroprocessor, which performs, in particular, the functions of associative self-learning and unconditional unraveling of the neural network.
The logical block of the neuroprocessor consists of elementary cells, in the electrical circuit of which a memristor connected to a diode-transistor logic component is used as a memory element. The topology of the logic block has a 3D-periodic design, which is a composition of CMOS layers and crossbars with memristor material. The manufacturing process of the logical unit is simple enough and can be adapted to existing production lines of electronic devices, since it is based on typical physical and chemical production methods. Memristor crossbars are manufactured by the method of reactive magnetron sputtering, which is combined with common standard CMOS technology.
Based on the logic block, the author suggests an electrical circuit that performs the functions of the known Hodgkin — Huxley neuron model. As examples of the realization of the processes of associative self-learning and the unconditional “unlearning” of the electronic logic unit, the principles of interaction of neurons in living objects during the elaboration of a conditioned reflex were used.
The operation of the logic block in the basic modes was investigated by the computer SPICE simulation method. For this purpose, model schemes of control drivers were developed, which were connected to the crossbar lines of the logical unit to generate information signals and set the operating mode of the logical unit. As simulation results, the stress and current diagrams of the combined memristor crossbar are obtained in the specified modes of operation of the device.
The main result achieved is the model of the neuron synapse realized by the analog operation of the memristor as a memory element of the logical block when it is read and written pulse. The change in the resistance of the memristors of the logic block during the pulse recording is shown and stable functioning during reading in the processes of associative self-learning and unconditional raising of the three-layer neural network.