Computational efficiency of memristor models in the hardware spiking neural network synaptic array simulation

About the authors:

Alexander N. Busygin, Cand. Sci. (Phys.-Math.), Senior Scientific Researcher, Nanomaterials and Nanoelectronics Laboratory, Center for Nature-Inspired Engineering, University of Tyumen, Tyumen, Russia; a.n.busygin@utmn.ru, https://orcid.org/0000-0002-3439-8067

Sergey Yu. Udovichenko, Dr. Sci. (Phys.-Math.), Professor, Department of Applied and Tech­nical Physics, School of Natural Sciences, University of Tyumen, Tyumen, Russia; Scientific Director of the Memristive Materials Laboratory, Center for Nature-Inspired Engineering, University of Tyumen, Tyumen, Russia; udotgu@mail.ru, https://orcid.org/0000-0003-3583-7081

Abstract:

To accelerate and reduce the cost of developing neuromorphic devices using memristors, simulation is essential. Unlike detailed physical and mathematical models of memristors, which require extensive calculation time due to the large number of partial differential equations, compact models containing a reduced number of equations exist. Due to the large number of memristors in synaptic arrays of hardware neural networks, memristor models must meet increased computational efficiency requirements to reduce calculation time. In this study, numerical simulations using the LTspice electrical circuit simulator were conducted to study the accuracy of reproducing the experimental current-voltage characteristics and the calculation time of models using smooth and piecewise linear functions. Model accuracy was quantified using the mean squared error, root mean squared error, and determination coefficient. Computation time was estimated by averaging over ten simulations of synaptic arrays with varying cell counts. For a model using smooth functions, an optimal number of parameters was found that yields the smallest deviation between the model and experimental current-voltage curves. Based on the balance between accuracy and computation time for simulating synaptic arrays in a hardware spiking neural network, piecewise linear memristor models were shown to be the most computationally efficient.

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